Research and Design of Video Acquisition and Storage System Based on DSP
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The design uses a dedicated video decoder chip, with the CPLD device as the control unit and peripheral interface, and FIFO as the buffer structure, which can effectively achieve high-speed parallel video signal acquisition and readout, with a simple overall circuit, high reliability, and high integration. The advantages of high, convenient interface, etc., can be applied to various video signal processing systems without changing the hardware circuit. The original very complex circuit design has been greatly simplified, and the original pure hardware design has become a mixed design of software and hardware, making the overall system design more flexible.
1, system hardware platform structure
The hardware structure of the system platform is shown in Figure 1. The entire system is divided into two parts, the image acquisition system and DSP-based main system. The former is based on SAA7110A/SAA7110 video decoder chip, CPLD by the complex programmable logic chip to achieve accurate sampling of high-speed video capture system; the latter is a general-purpose digital signal processing system, which mainly includes: 64KWORD program memory, 64KWORD data memory, DSP, Clock generation circuit, serial interface and the corresponding level conversion circuit.
The work flow of the system is that, firstly, the image acquisition data of the designated area is accurately collected by the image acquisition system according to the QCIF format, and temporarily stored in the frame memory FIFO; the data temporarily stored in the FIFO is read into the data memory of the DSP by the DSP. , H.263-based video data compression is performed together with the original several frames of image data; then the compressed video data is smoothly output from the serial interface by the DSP, and transmitted to the remote monitoring center by the ordinary MODEM or ADSL MODEM. The PC in the monitoring center will decode the received data and display the restored video image or broadcast based on WEB.
2. Video signal acquisition system 2.1 Basic features of video signal acquisition system
The general video signal acquisition system is generally composed of video signal by clamping amplification, synchronization signal separation, luminance/chrominance signal separation and A/D conversion. The sampling data is output to the data bus according to certain timing and bus requirements. This completes the decoding of the video signal. The memory in the figure serves as a frame-sampling buffer memory and can accommodate bus interfaces with different busses, output formats, and timing requirements.
Video signal acquisition system is a special case of high-speed data acquisition system. In the past, video signal acquisition systems used small-scale digital and analog devices to implement high-speed operational amplification, synchronization signal separation, luminance/chroma separation, high-speed A/D conversion, phase-locked loop, and sequential logic control circuits. However, due to the system's sampling frequency and operating clock of up to tens of megahertz, low device integration, complicated wiring, and large inter-stage and device-to-device coupling interference, development and debugging are very difficult; on the other hand, accurate sampling is required. The purpose is that the sampling clock needs to form a synchronization relationship with the input video signal. Therefore, using the separated synchronization signal and the system sampling clock to lock the phase to generate an accurate and synchronous sampling clock becomes another difficult point in the design and debugging process. At the same time, through the programmable control of brightness, chroma, contrast, and video pre-amplification gain, the intelligence of the video signal acquisition is difficult to complete in the past. On this point, we have had a deep understanding of the initial development of the system [1].
Based on the above considerations, the system uses the SAA7110A as an input front-end video sampling processor for a video surveillance system.
2.2 video image acquisition system design
The SAA7110/SAA7110A are highly integrated, feature-rich, large-scale video decoding integrated circuits [2]. It is packaged in PLCC68 and integrates two 8-bit analog-to-digital converters for video signal sampling, clock generation circuits and peripheral circuits such as brightness, contrast and saturation control. It replaces the original discrete circuit and greatly reduces The workload of the small system design, and through the built-in a large number of functional circuits and control registers to achieve flexible configuration of the function. The SAA7110/SAA7110A can be used in areas such as desktop video, multimedia, digital televisions, image processing, video telephony, video image acquisition systems, and more.
The control bus interface of the SAA7110/SAA7110A is the I2C bus. The SAA7110/SAA7110A is a slave device of the I2C bus. According to the level of the SA pin, the device read/write address can be set to 9CH/9DH (W/R, SA=0) or 9DH/9FH (W/R, SA=, respectively). 1). It has a total of 47 internal registers that control the decoders (00H to 19H) and video interfaces (20H to 34H). Reading and writing the above-mentioned register in the slice through I2C bus, can finish input channel choice, level clamp and gain control, brightness, chroma and saturation control and so on.
However, there is a problem that must be solved. That is, the DSP chip does not have an I2C bus interface built in. For this purpose, the system proposes and uses a software emulation of two programmable I/O pins of a DSP chip to implement the I2C bus control method. . Due to the limitation of only 64 KB in the storage space of the C2000 program, in order to reduce the scale of the I2C bus control simulation software, the simulation software is completed in assembly language, which brings considerable difficulty and workload to the design of the system.
3, system experiment and simulation
In the design of real-time systems, synchronization and accurate sampling are two crucial issues. They are directly related to the success or failure of the system design.
Because the two clock signals LCC and LCC2 output by the SAA7110A are synchronized with the sampling clock and the data output clock, they can serve as a clock for data storage control in the sampling data interface control subsystem and a synchronous clock for performing various functions, and the system does not need to generate or The use of additional clock signals avoids synchronization and phase-locking problems between the external clock, the sampling clock, and the video signal. This ensures the synchronization of the entire system and greatly reduces the complexity of the system design. The line valid signal HREF, line sync signal HS, field sync signal VS, odd-even field signal ODD, and system sampling clock LCC and half-clocked clock LCC2 outputted by the SAA7110A are processed to obtain current sampling position information, and The time, spatial position, and accuracy requirements for sampling are achieved along with the generation of frame memory addresses, chip select, and write control signals.
According to DSP chip read timing (as shown in Figure 2), write timing, SAA7110A chip HREF signal timing, Vertical signal timing (as shown in Figure 3) and Horizontal signal timing requirements, in accordance with the collection of QCIF (176 × 144) format The needs of the elephant, designed CPLD accurate sampling of the sequential logic (as shown in Figure 4).
(a) Sequential logic for accurate sampling of CPLDs; (b) Performing 32-times enlargement of (b) above The CPLD results in timing simulations that fully meet predetermined precision sampling requirements. Really accurate sampling with the correct ratio relationship is achieved with good results.
4 Conclusion
In the design of DSP-based video image acquisition system, the use of video-specific decoding A/D chips and CPLDs for control and interface design can effectively achieve high-speed parallel video signal acquisition and readout, with overall The advantages of simple circuit, high reliability, high integration, convenient interface, etc., can be applied to various video signal processing systems without changing the hardware circuit. This simplifies the original and very complicated circuit design, making the overall system design more flexible.
